Матрица конфигураций OrCAD и Allegro

OrCAD Standard и OrCAD Professional являются минимальной и средней конфигурацией САПР печатных плат Cadence (на базе технологий Allegro) и позволяют добавлять опции OrCAD.
Allegro PCB Artist включает в себя возможности Professional, добавляет несколько важных функций, является базовой конфигурацией Allegro, однако не позволяет наращивать функционал опциями Allegro.
Allegro PCB Designer включает в себя PCB Artist и позволяет добавлять опции Allegro.
Allegro PCB Venture включает в себя PCB Designer и опции: High Speed, Miniaturization, Design Planning и Routing, и позволяет добавлять другие опции Allegro.
Allegro Sigrity Aurora включает в себя частично PCB Designer, за исключением редактора схем и экспорта производственных файлов, но добавляет функции анализа SI/PI и IR Drop прямо в окне PCB Designer.

ФУНКЦИИORCADALLEGRO
Плавающая сетевая лицензияStandardArtist
12 месяцев технического обслуживания, включенного в стоимость покупкиStandardArtist
ВВОД СХЕМ + УПРАВЛЕНИЕ ДАННЫМИ
Схемный редактор CaptureStandardArtist
Система управления компонентами CISDesigner
Схемный редактор System CaptureArtist
Старый схемный редактор DE HDLDesigner
Flexible Window layoutStandardArtist
Graphical, flat and hierarchical page editor and Picture block hierarchyStandardArtist
OrCAD PSpice AD Basics — Restricted Capacity — see PSpice Matrix belowStandardAllegro PSpice System Designer
Net Groups — Complex bus definitionStandardArtist
AutoWireStandardArtist
44000 схематических символовStandardArtist
Coloured Components / netsStandardArtist
Tcl TK scripting supportStandardArtist
 Online design rule check including custom DRC capability and Waive DRCStandardArtist
Forward and back-annotation of properties / pin-and-gate swapsStandardArtist
Schematic Part and Library editorStandardArtist
Cross-probing and cross-placingStandardArtist
FPGA design-in / pin import & exportStandardArtist
Multiple PCB netlist interfaces — New Design Sync for Cadence FlowStandardArtist
Part Search Providers UltraLibrarian and Samacsys (Symbol, Footprint 3d Step Model)StandardArtist
Property editor for pins, components, netsStandardArtist
OrCAD SigXplorer SI AnalysisStandardArtist
Intelligent PDF creationStandardArtist
Advanced AnnotationStandardArtist
Design Compare (detail and Graphical)StandardArtist
Default Demo designsStandardArtist
Extended PreferencesStandardArtist
Export ISCF (Intel Schematic Connectivity Format)StandardArtist
Export / Import XMLStandardArtist
Altium Importer Schematic (PCB also available)StandardArtist
Eagle Importer Schematic (PCB also available)StandardArtist
Constraint ManagerStandardArtist
Component Information SystemCIS optionDesigner
Windows ODBC compatible formatCIS optionDesigner
Interface to relational database and management systemsCIS optionDesigner
Database query for part selection and parametric propertiesCIS optionDesigner
Schematic and BOM Variants Manager (Parts not Fitted and more).CIS optionDesigner
Component Information Portal (CIP), Access to Mouser, Digikey, Future, FarnellCIS Option + CIP E OptionCIP E Option
PCB РЕДАКТОР
Spacing, Same net, Netclass and Class to Class rulesStandardArtist
Physical Constraint RulesStandardArtist
DesignTrue DFM WizardStandardArtist
Design for Test ChecksStandardArtist
Design For Assembly ChecksStandardArtist
Design For Fabrication ChecksStandardArtist
Version ControlStandardArtist
Component Lead EditorStandardArtist
Import File ManagerStandardArtist
DFM Pad Entry / Exit RulesStandardArtist
Dynamic pad suppression / Unused Pad removalStandardArtist
Cross Section EditorStandardArtist
Padstack Editor IPC2581 CompliantStandardArtist
Application Mode (General, Etch, Placement)StandardArtist
Application Mode (shape)StandardArtist
Full Skill language SupportStandardArtist
Customisable Visibility PaneStandardArtist
Dynamic Shape Pin Connection By Layer (Global/Shape/Pin/Layer)StandardArtist
Dynamic Cross Hatch ShapesStandardArtist
Dynamic Shapes (dynamic copper pours) Plow and HealStandardArtist
Move with autoroute adjust (Slide)StandardArtist
Multiple placement options, manual, quickplace, auto and roomStandardArtist
Alignment x and y for components and modulesStandardArtist
Dynamic rat suppressionStandardArtist
Fan-out generatorsStandardArtist
Interactive Routing using Working Layer (layer selection popup)StandardArtist
Group route Bus Route and via patternsStandardArtist
Line FatteningStandardArtist
Differential Pair Static Phase Control rulesStandardArtist
Differential Pairs Physical rules and routingStandardArtist
Blind Buried Single Click multiple via instantiationStandardArtist
Push, Shove and Hug interactive editingStandardArtist
Curve RoutingStandardArtist
Snake Routing for Hex pattern ICsStandardArtist
Auto Finish (Route Completion Tool)StandardArtist
Scribble Sketch RoutingStandardArtist
Route cleanup, optimization (Glossing)StandardArtist
Embedded net namesStandardArtist
Split ViewStandardArtist
Through Board Transparency (OpenGL)StandardArtist
Flip BoardStandardArtist
Excellon NC Drill File exportStandardArtist
Gerber 274X, 274D artwork OutputStandardArtist
IPC2581 Import / ExportStandardArtist
Mentor ODB++ and universal viewerStandardArtist
Impedance CalculatorStandardArtist
Interactive / Automatic Silkscreen generationStandardArtist
Import Altium PCB (schematic also available)StandardArtist
Import EAGLE PCB (schematic also available)StandardArtist
Import PADS & PCADStandardArtist
Import IFF RF ShapesStandardArtist
Import Export DXFStandardArtist
Import Export IDFStandardArtist
Export Intelligent PDFStandardArtist
MCAD/ECAD Incremental design data exchange (IDX)StandardArtist
3D/2D CrossprobingStandardArtist
STEP 3D Clash DetectStandardArtist
STEP 3D viewer for selected item or complete PCBStandardArtist
STEP 3D Canvas ControlsStandardArtist
STEP 3D Import ExportStandardArtist
STEP 3D Canvas Highlight SelectionsStandardArtist
Manual Design For Test (DFT) / Test PrepStandardArtist
Associative DimensioningStandardArtist
Autoroute Nets by Pick, 6- Signal Layers, no layer limit or Pin LimitStandardArtist
Autoroute Automatic, 6- Signal Layers, no layer limit or Pin LimitProfessionalArtist
Net Scheduling, T-Point rules (pin to T-point), T-Point definitionProfessionalArtist
Constraint Regions, region based rules (Rigid-Flex; BGA regions)ProfessionalArtist
Propagation delay rules (Relative) for nets or groupsProfessionalArtist
Propagation delay rules (Min/Max) for nets or groupsProfessionalArtist
Total Etch Length — Max/Min LengthProfessionalArtist
Extended (X)net rulesProfessionalArtist
Layer set rulesProfessionalArtist
Pin Pair rulesProfessionalArtist
Delay TuningProfessionalArtist
Dynamic Heads-up Display for critical rulesProfessionalArtist
Hug Contour routing (Flex)ProfessionalArtist
Segment over void detectionProfessionalArtist
Spread lines between voidsProfessionalArtist
Shape based curve fillet support, tapered tracesProfessionalArtist
Placement replication, template based design reuseProfessionalArtist
Via array / Shielding — Shape and Trace basedProfessionalArtist
Rigid Flexi Zone ManagementProfessionalArtist
Dynamic Zone PlacementProfessionalArtist
Inter Layer Checks for Rigid FlexiProfessionalArtist
3D BendingProfessionalArtist
High Speed Analysis Impedance WorkflowProfessionalArtist
High Speed Analysis Coupling WorkflowProfessionalArtist
Placement VisionProfessionalArtist
Route VisionProfessionalArtist
Differential Pair Dynamic Phase Control rulesProfessionalArtist
Package Pin Delay (for die-2-die delay) rulesProfessionalArtist
Z-Axis delay feedbackProfessionalArtist
BackdrillingProfessionalArtist
Automatic Design For Test (DFT) / Test PrepProfessionalArtist
PanelizationProfessionalArtist
Match / Max Via Count rulesArtist
Offset RoutingDesigner
Design planning — Create hierarchical BundlesDesigner
Design planning — Create, Edit Flows, Assign Flows to LayersDesigner
Dynamic Shape based curve fillet support, tapered tracesArtist
CAD Translators — Import Mentor BoardstationDesigner
RF TracesArtist
Design Link (Link Constraints from multiple boards)Artist
Design For Assembly — Placement ControlDesigner
Electrical Constraint Set (ECSet) ReuseDesigner
Chip on BoardDesigner
Allegro Constraint CompilerHigh-Speed Option
High Speed Return Path DRCHigh-Speed Option
High Speed IR Drop Analysis Workflow (load capability)High-Speed Option
High Speed Reflection Analysis Workflow (load capability)High-Speed Option
Timing Environment — Auto Delay Tune (AiDT), Auto Phase Tune (AiPT), Remove TuningHigh-Speed Option
Tabbed RoutingHigh-Speed Option
Electrical Constraint rule set (ECSets) / Topology ApplyHigh-Speed Option
Electrical rules (Reflection, Timing, Crosstalk)High-Speed Option
Advanced Constraints (formulas, relational)High-Speed Option
Fibre Weave Effect Zig Zag Auto InteractiveHigh-Speed Option
High Speed Static Phase Via Transition DRCHigh-Speed Option
Via Voiding Differential PairsHigh-Speed Option
Single net Return Paths ViasHigh-Speed Option
High Speed Differential Pair Return Path ViasHigh-Speed Option
High Speed Intra Differential Pairs Spacing RulesHigh-Speed Option
High Speed Via StructuresHigh-Speed Option
High Speed Inductance Via StructuresHigh-Speed Option
Constraint Manager: HDI rule setMiniaturization Option
Micro-via and associated spacing, stacking and via-in-pad rulesMiniaturization Option
Constraint driven HDI design flowMiniaturization Option
HDI micro-via stack editingMiniaturization Option
Manufacturing rule support for embedding componentsMiniaturization Option
Embed components on inner layersMiniaturization Option
Support for Cavities on inner layersMiniaturization Option
Support for Vertically placed components on inner layersMiniaturization Option
Soldermask for embedded componentsMiniaturization Option
Support for copy and swap embedded componentsMiniaturization Option
Dual Side Contact Embedded ComponentsMiniaturization Option
Design Planning — Plan Spatial Feasibility analysis & feedbackDesign Planning Option
Design Planning — Generate Topological PlanDesign Planning Option
Design Planning — Convert Topological plan to traces (CLINES)Design Planning Option
Auto Interactive Break-out (AiBT)Design Planning Option
Auto Connect (Breakout, Connect, Compress, Spread, Nudge, Push)Design Planning Option
Symphony Team Design New Option, one board with multiple designers in real timeSymphony Team Design Option
Swap pins on a FPGA (based on FPGA rules) in PCB EditorFPGA System Planner
Reoptimize pins on a FPGA (using FPGA rules)FPGA System Planner
Parameterized RF etch elementsAnalog / RF Option
Asymmetrical ClearancesAnalog / RF Option
RF Etch elements editingAnalog / RF Option
Bi-Directional interface with Agilent ADSAnalog / RF Option
ADS schematics Import Agilent into DE-HDLAnalog / RF Option
Layout-driven RF design creation Analog / RF Option
Flexible Shape EditorAnalog / RF Option
PSpice SIMULATION
Bias Point, DC sweep, AC sweep & transient analysis (with Temperature)PSpice ADPSpice AD
Parametric AnalysisPSpice ADPSpice AD
Learning PSpice Free TemplatesPSpice ADPSpice AD
Analog behavioural modellingPSpice ADPSpice AD
Stimulus editorPSpice ADPSpice AD
Model Editor for device characterizationPSpice ADPSpice AD
Interactive waveform viewer & analyzerPSpice ADPSpice AD
IBIS / DML model supportPSpice ADPSpice AD
Monte Carlo: Statistical circuit behaviour and yield (Worst Case)PSpice ADPSpice AD
Bias point voltages, currents and power display on schematicPSpice ADPSpice AD
Example Design Simple Circuit 1PSpice ADPSpice AD
Example Design Simple Circuit 2PSpice ADPSpice AD
Example Design Simple Circuit 3PSpice ADPSpice AD
Example Design Simple Circuit 4PSpice ADPSpice AD
Example Design Simple Circuit 5PSpice ADPSpice AD
 Example Design Simple Circuit 6Spice ADPSpice AD
Example Design Simple Circuit 7PSpice ADPSpice AD
Sensitivity: Identifies critical circuit componentsAdvanced AnalysisAdvanced Analysis
Optimizer: Optimizes key circuit componentsAdvanced AnalysisAdvanced Analysis
Monte Carlo: Statistical circuit behaviour and yield multiple measurementsAdvanced AnalysisAdvanced Analysis
Smoke: Detects component stressAdvanced AnalysisAdvanced Analysis
Parametric Plotter: Examine solution through nested sweepsAdvanced AnalysisAdvanced Analysis
Optimize Circuits through Curve or Parameter FitAdvanced AnalysisAdvanced Analysis
SIGNAL INTEGRITY
Pre-route signal integrity analysisStandardArtist
Pre-route & Post-route signal integrity analysisProfessionalAurora
Graphical topology definition and explorationStandardArtist
Interactive waveform viewerStandardArtist
Macro modelling support (DML)StandardArtist
IBIS 5.0 supportStandardArtist
IBIS ICM model supportStandardArtist
Spectre-to-DMLStandardArtist
HSPICE-to-IBISStandardArtist
Lossy transmission linesStandardArtist
Coupled (3 net) simulation Pre-RouteStandardArtist
Differential pair exploration and simulationStandardArtist
Standalone AutoRouterProfessionalArtist
6 Signal Layers at a time (no board layer limit or pin limit)ProfessionalArtist
Shape-based or Gridded routingProfessionalArtist
SMD FanoutProfessionalArtist
Physical Trace Width by Net and Net ClassesProfessionalArtist
45-degree / Memory Pattern RoutingProfessionalArtist
Interactive Routing with Shoving and PlowingProfessionalArtist
Interactive FloorplanningProfessionalArtist
Online Design Rule CheckingProfessionalArtist
Flip, Rotate, Align, Push, and Move ComponentsProfessionalArtist
Placement Density AnalysisProfessionalArtist
Min/Max, matched length rules based autoroutingArtist
Pin-pair rules, Area rules based autoroutingArtist
Crosstalk controls, parallelism rules based autoroutingArtist
Differential Pair Autorouting, Automatic net shieldingArtist
High-speed rules-based autoroutingArtist
256 signal layer limitOrCAD AI OptionRouting Option
DFM rules-based autorouting automatic trace spreading, via reduction and miteringRouting Option
Spacing Net Class — Class RulesRouting Option
Via Rules by Net and Net ClassRouting Option
Mircovia features including Plural and Stacked microviasRouting Option
Auto Test Point Generation and Clearance RulesRouting Option
Layer-specific rules-based autoroutingRouting Option

Конфигурации PSpice

Category/FeaturePSpice AD BasicPSpice PSpice
Designer Plus
Simulation CapacityDesign should have less than or equal to 250 nodes or 250 devices and such designs can be simulated
—-upto 1,000,000 data point for transient analysis
—-upto 10,000 data point for AC or DC sweep analysis
No limitNo limit
Device
Analog DevicesAll (Except BSIM 3.3 and BSIM 4 devices, Magnetic Core, IGBT,Tlines, DMI models)AllAll
DigitalAllAllAll
Analysis Types
DCYesYesYes
ACYesYesYes
TransientYesYesYes
Parametric SweepYesYesYes
Check Point RestartYesYesYes
Monte CarloYesYesYes
Worst caseYesYesYes
Digital Worst CaseYesYesYes
Auto ConvergenceYesYesYes
OPYesYesYes
Transfer FunctionYesYesYes
Sensitivity AnalysisYesYesYes
SPEED ModeYesYesYes
Advance ConvergenceYesYesYes
Waveform Analysis
MeasurementYesYesYes
Performance AnalysisNoYesYes
Advanced Tools(FRA,Core loss)YesYesYes
FFTYesYesYes
Utilities
Model EditorNoYesYes
Stimulus EditorNoYesYes
Magnetic Parts EditorNoYesYes
Modeling ApplicationYesYesYes
Advanced Analyses
SmokeNoYesYes
OptimizerNoNoYes
SensitivityNoNoYes
Monte CarloNoNoYes
Parametric PlotterNoNoYes
PSpice-MATLAB Interface
Co-SimulationNoNoYes
Visualization NoNoYes
FunctionsNoNoYes