Cadence PCB Suite матрица конфигураций OrCAD и Allegro

ФУНКЦИИSTANDARD PROFESSIONALALLEGRO
Плавающая сетевая лицензия+++
12 месяцев технического обслуживания, включенного в стоимость покупки+++
ВВОД СХЕМ + УПРАВЛЕНИЕ ДАННЫМИ
Flexible Window layout+++
Graphical, flat and hierarchical page editor and Picture block hierarchy+++
OrCAD PSpice AD Basics — Restricted Capacity — see PSpice Matrix below++Allegro PSpice System Designer
Net Groups — Complex bus definition+++
AutoWire+++
44000 схематических символов+++
Coloured Components / nets+++
Tcl TK scripting support+++
 Online design rule check including custom DRC capability and Waive DRC+++
Forward and back-annotation of properties / pin-and-gate swaps+++
Schematic Part and Library editor+++
Cross-probing and cross-placing+++
FPGA design-in / pin import & export+++
Multiple PCB netlist interfaces — New Design Sync for Cadence Flow+++
Part Search Providers UltraLibrarian and Samacsys (Symbol, Footprint 3d Step Model)+++
Property editor for pins, components, nets+++
OrCAD SigXplorer SI Analysis+++
Intelligent PDF creation+++
Advanced Annotation+++
Design Compare (detail and Graphical)+++
Default Demo designs+++
 Extended Preferences+++
Export ISCF (Intel Schematic Connectivity Format)+++
Export / Import XML+++
Altium Importer Schematic (PCB also available)+++
Eagle Importer Schematic (PCB also available)+++
Constraint Manager+++
Component Information SystemCIS optionCIS option+
Windows ODBC compatible formatCIS optionCIS option+
Interface to relational database and management systemsCIS optionCIS option+
Database query for part selection and parametric propertiesCIS optionCIS option+
Schematic and BOM Variants Manager (Parts not Fitted and more).CIS optionCIS option+
Component Information Portal (CIP), Access to Mouser, Digikey, Future, FarnellCIS Option + CIP E OptionCIS Option + CIP E OptionCIP E Option
PCB РЕДАКТОР
Spacing, Same net, Netclass and Class to Class rules+++
Physical Constraint Rules+++
DesignTrue DFM Wizard+++
Design for Test Checks+++
Design For Assembly Checks+++
Design For Fabrication Checks+++
Version Control+++
Component Lead Editor+++
 Import File Manager+++
DFM Pad Entry / Exit Rules+++
Dynamic pad suppression / Unused Pad removal+++
Cross Section Editor+++
Padstack Editor IPC2581 Compliant+++
Application Mode (General, Etch, Placement)+++
Application Mode (shape)+++
Full Skill Support+++
Customisable Visibility Pane+++
Dynamic Shape Pin Connection By Layer (Global/Shape/Pin/Layer)+++
Dynamic Cross Hatch Shapes+++
Dynamic Shapes (dynamic copper pours) Plow and Heal+++
Move with autoroute adjust (Slide)+++
Multiple placement options, manual, quickplace, auto and room+++
Alignment x and y for components and modules+++
Dynamic rat suppression+++
Fan-out generators+++
Interactive Routing using Working Layer (layer selection popup)+++
Group route Bus Route and via patterns+++
Line Fattening+++
Differential Pair Static Phase Control rules+++
Differential Pairs Physical rules and routing+++
Blind Buried Single Click multiple via instantiation+++
Push, Shove and Hug interactive editing+++
Curve Routing+++
Snake Routing for Hex pattern ICs+++
Auto Finish (Route Completion Tool)+++
Scribble Sketch Routing+++
Route cleanup, optimization (Glossing)+++
Embedded net names+++
Split View+++
Through Board Transparency (OpenGL)+++
Flip Board+++
Excellon NC Drill File export+++
Gerber 274X, 274D artwork Output+++
IPC2581 Import / Export+++
Mentor ODB++ and universal viewer+++
Impedance Calculator+++
Interactive / Automatic Silkscreen generation+++
Import Altium PCB (schematic also available)+++
Import EAGLE PCB (schematic also available)+++
Import PADS & PCAD+++
Import IFF RF Shapes+++
Import Export DXF+++
Import Export IDF+++
Export Intelligent PDF+++
MCAD/ECAD Incremental design data exchange (IDX)+++
3D/2D Crossprobing+++
STEP 3D Clash Detect+++
STEP 3D viewer for selected item or complete PCB+++
STEP 3D Canvas Controls+++
STEP 3D Import Export+++
STEP 3D Canvas Highlight Selections+++
Manual Design For Test (DFT) / Test Prep+++
Associative Dimensioning+++
Autoroute Nets by Pick, 6- Signal Layers, no layer limit or Pin Limit+++
Autoroute Automatic, 6- Signal Layers, no layer limit or Pin Limit++
Net Scheduling, T-Point rules (pin to T-point), T-Point definition++
Constraint Regions, region based rules (Rigid-Flex; BGA regions)++
Propagation delay rules (Relative) for nets or groups++
Propagation delay rules (Min/Max) for nets or groups++
Total Etch Length — Max/Min Length++
Extended (X)net rules++
Layer set rules++
Pin Pair rules++
Delay Tuning++
Dynamic Heads-up Display for critical rules++
Hug Contour routing (Flex)++
Segment over void detection++
Spread lines between voids++
Shape based curve fillet support, tapered traces++
Placement replication, template based design reuse++
Via array / Shielding — Shape and Trace based++
Rigid Flexi Zone Management++
Dynamic Zone Placement++
Inter Layer Checks for Rigid Flexi++
3D Bending++
High Speed Analysis Impedance Workflow++
High Speed Analysis Coupling Workflow++
Placement Vision++
Route Vision++
Differential Pair Dynamic Phase Control rules++
Package Pin Delay (for die-2-die delay) rules++
Z-Axis delay feedback++
Backdrilling++
Automatic Design For Test (DFT) / Test Prep++
Panelization++
Match / Max Via Count rules+
Offset Routing+
Design planning — Create hierarchical Bundles+
Design planning — Create, Edit Flows, Assign Flows to Layers+
Dynamic Shape based curve fillet support, tapered traces+
CAD Translators — Import Mentor Boardstation+
RF Traces+
Design Link (Link Constraints from multiple boards)+
Design For Assembly — Placement Control+
Electrical Constraint Set (ECSet) Reuse+
Chip on Board+
Allegro Constraint CompilerPCB High-Speed Option
High Speed Return Path DRCPCB High-Speed Option
High Speed IR Drop Analysis Workflow (load capability)PCB High-Speed Option
High Speed Reflection Analysis Workflow (load capability)PCB High-Speed Option
Timing Environment — Auto Delay Tune (AiDT), Auto Phase Tune (AiPT), Remove TuningPCB High-Speed Option
Tabbed RoutingPCB High-Speed Option
Electrical Constraint rule set (ECSets) / Topology ApplyPCB High-Speed Option
Electrical rules (Reflection, Timing, Crosstalk)PCB High-Speed Option
Advanced Constraints (formulas, relational)PCB High-Speed Option
Fibre Weave Effect Zig Zag Auto InteractivePCB High-Speed Option
High Speed Static Phase Via Transition DRCPCB High-Speed Option
Via Voiding Differential PairsPCB High-Speed Option
Single net Return Paths ViasPCB High-Speed Option
High Speed Differential Pair Return Path ViasPCB High-Speed Option
High Speed Intra Differential Pairs Spacing RulesPCB High-Speed Option
High Speed Via StructuresPCB High-Speed Option
High Speed Inductance Via StructuresPCB High-Speed Option
Constraint Manager: HDI rule setMiniaturization Option
Micro-via and associated spacing, stacking and via-in-pad rulesMiniaturization Option
Constraint driven HDI design flowMiniaturization Option
HDI micro-via stack editingMiniaturization Option
Manufacturing rule support for embedding componentsMiniaturization Option
Embed components on inner layersMiniaturization Option
Support for Cavities on inner layersMiniaturization Option
Support for Vertically placed components on inner layersMiniaturization Option
Soldermask for embedded componentsMiniaturization Option
Support for copy and swap embedded componentsMiniaturization Option
Dual Side Contact Embedded ComponentsMiniaturization Option
Design Planning — Plan Spatial Feasibility analysis & feedbackDesign Planning Option
Design Planning — Generate Topological PlanDesign Planning Option
Design Planning — Convert Topological plan to traces (CLINES)Design Planning Option
Auto Interactive Break-out (AiBT)Design Planning Option
Auto Connect (Breakout, Connect, Compress, Spread, Nudge, Push)Design Planning Option
Symphony Team Design New Option, one board with multiple designers in real timeSymphony Team Design Option
Swap pins on a FPGA (based on FPGA rules) in PCB EditorFPGA System Planner
Reoptimize pins on a FPGA (using FPGA rules)FPGA System Planner
Parameterized RF etch elementsPCB Analog / RF Option
Asymmetrical ClearancesPCB Analog / RF Option
RF Etch elements editingPCB Analog / RF Option
Bi-Directional interface with Agilent ADSPCB Analog / RF Option
ADS schematics Import Agilent into DE-HDLPCB Analog / RF Option
Layout-driven RF design creationPCB Analog / RF Option
Flexible Shape EditorPCB Analog / RF Option
PSpice SIMULATION
 Bias Point, DC sweep, AC sweep & transient analysis (with Temperature)PSpice ADPSpice ADPSpice AD
Parametric AnalysisPSpice ADPSpice ADPSpice AD
Learning PSpice Free TemplatesPSpice ADPSpice ADPSpice AD
Analog behavioural modellingPSpice ADPSpice ADPSpice AD
Stimulus editorPSpice ADPSpice ADPSpice AD
Model Editor for device characterizationPSpice ADPSpice ADPSpice AD
Interactive waveform viewer & analyzerPSpice ADPSpice ADPSpice AD
IBIS / DML model supportPSpice ADPSpice ADPSpice AD
Monte Carlo: Statistical circuit behaviour and yield (Worst Case)PSpice ADPSpice ADPSpice AD
Bias point voltages, currents and power display on schematicPSpice ADPSpice ADPSpice AD
Example Design Simple Circuit 1PSpice ADPSpice ADPSpice AD
Example Design Simple Circuit 2PSpice ADPSpice ADPSpice AD
Example Design Simple Circuit 3PSpice ADPSpice ADPSpice AD
Example Design Simple Circuit 4PSpice ADPSpice ADPSpice AD
Example Design Simple Circuit 5PSpice ADPSpice ADPSpice AD
 Example Design Simple Circuit 6Spice ADPSpice ADPSpice AD
Example Design Simple Circuit 7PSpice ADPSpice ADPSpice AD
Sensitivity: Identifies critical circuit componentsAdvanced AnalysisAdvanced AnalysisAdvanced Analysis
Optimizer: Optimizes key circuit componentsAdvanced AnalysisAdvanced AnalysisAdvanced Analysis
Monte Carlo: Statistical circuit behaviour and yield multiple measurementsAdvanced AnalysisAdvanced AnalysisAdvanced Analysis
Smoke: Detects component stressAdvanced AnalysisAdvanced AnalysisAdvanced Analysis
Parametric Plotter: Examine solution through nested sweepsAdvanced AnalysisAdvanced AnalysisAdvanced Analysis
Optimize Circuits through Curve or Parameter FitAdvanced AnalysisAdvanced AnalysisAdvanced Analysis
SIGNAL INTEGRITY
Pre- & Post-route signal integrity analysisPre Route++
Graphical topology definition and explorationPre Route++
Interactive waveform viewerPre Route++
Macro modelling support (DML)Pre Route++
IBIS 5.0 supportPre Route++
IBIS ICM model supportPre Route++
Spectre-to-DMLPre Route++
HSPICE-to-IBISPre Route++
Lossy transmission linesPre Route++
Coupled (3 net) simulation Pre-RoutePre Route++
Differential pair exploration and simulationPre Route++
StandardProfessionalAllegro
Standalone AutoRouter++
6 Signal Layers at a time (no board layer limit or pin limit)++
Shape-based or Gridded routing++
SMD Fanout++
Physical Trace Width by Net and Net Classes++
45-degree / Memory Pattern Routing++
Interactive Routing with Shoving and Plowing++
Interactive Floorplanning++
Online Design Rule Checking++
Flip, Rotate, Align, Push, and Move Components++
Placement Density Analysis++
Min/Max, matched length rules based autorouting+
Pin-pair rules, Area rules based autorouting+
Crosstalk controls, parallelism rules based autorouting+
Differential Pair Autorouting, Automatic net shielding+
High-speed rules-based autorouting+
256 signal layer limitOrCAD AI OptionPCB AutoRouting Option
DFM rules-based autorouting automatic trace spreading, via reduction and miteringPCB AutoRouting Option
Spacing Net Class — Class RulesPCB AutoRouting Option
Via Rules by Net and Net ClassPCB AutoRouting Option
Mircovia features including Plural and Stacked microviasPCB AutoRouting Option
Auto Test Point Generation and Clearance RulesPCB AutoRouting Option
Layer-specific rules-based autoroutingPCB AutoRouting Option

PSpice Tiers

Category/FeaturePSpice AD BasicPSpice ADOrCAD PSpice
Designer Plus
Simulation CapacityDesign should have less than or equal to 250 nodes or 250 devices and such designs can be simulated
—-upto 1,000,000 data point for transient analysis
—-upto 10,000 data point for AC or DC sweep analysis
No limitNo limit
Device
Analog DevicesAll (Except BSIM 3.3 and BSIM 4 devices, Magnetic Core, IGBT,Tlines, DMI models)AllAll
DigitalAllAllAll
Analysis Types
DCYesYesYes
ACYesYesYes
TransientYesYesYes
Parametric SweepYesYesYes
Check Point RestartYesYesYes
Monte CarloYesYesYes
Worst caseYesYesYes
Digital Worst CaseYesYesYes
Auto ConvergenceYesYesYes
OPYesYesYes
Transfer FunctionYesYesYes
Sensitivity AnalysisYesYesYes
SPEED ModeYesYesYes
Advance ConvergenceYesYesYes
Waveform Analysis
MeasurementYesYesYes
Performance AnalysisNoYesYes
Advanced Tools(FRA,Core loss)YesYesYes
FFTYesYesYes
Utilities
Model EditorNoYesYes
Stimulus EditorNoYesYes
Magnetic Parts EditorNoYesYes
Modeling ApplicationYesYesYes
Advanced Analyses
SmokeNoYesYes
OptimizerNoNoYes
SensitivityNoNoYes
Monte CarloNoNoYes
Parametric PlotterNoNoYes
PSpice-MATLAB Interface
Co-SimulationNoNoYes
Visualization NoNoYes
FunctionsNoNoYes